1. Field of the Invention
The present invention relates to a power semiconductor device and a manufacturing method thereof, and more particularly, to a power semiconductor device with an electrostatic discharge structure and a manufacturing method thereof.
2. Description of the Prior Art
Power metal-oxide-semiconductor (MOS) transistor devices have conductive properties of high voltage and high current, and thus are easily damaged due to electrostatic discharge (ESD) pulses. To obtain a lower threshold voltage in more current integrated circuit manufacturing processes, thickness of a gate oxide layer of the power MOS transistor device is reduced. Therefore, the power MOS transistor device is easily damaged by ESD pulses caused by static electricity or other uncontrollable factors. To solve this problem, ESD devices are combined with the power MOS transistor device to protect the power MOS transistor device from being damaged. In existing techniques for fabricating the power MOS transistor device, a process used to fabricate the ESD devices is performed after the power MOS transistor device is fabricated. Accordingly, extra processes are required, which raise the fabricating cost.
Please refer to FIG. 1, which illustrates a cross-sectional view of a power semiconductor device according to the prior art. As shown in FIG. 1, the power semiconductor device 10 according to the prior art includes a plurality of trench type transistor devices 14 and a plurality of ESD devices 16 formed on a semiconductor substrate 12. The ESD devices 16 are formed by the following steps. A polycrystalline silicon layer 18 is formed, and then a P-ion implantation process and an N-ion implantation process are performed on the polycrystalline silicon layer 18 in sequence to form a plurality of P-doped regions 20 and a plurality of N-doped regions 22. The P-doped regions 20 and the N-doped regions 22 are alternately connected to each other in sequence. Any P-doped region 20 and the N-doped region 22 adjacent thereto form an ESD device 16 with a P-N junction, and the ESD devices 16 are connected between a gate electrode and a drain electrode of the trench type transistor device in series.
As mentioned above, conventional ESD devices are formed by doping the polycrystalline silicon layer. Since the lattice structure of the polycrystalline silicon layer limits current transmitted therein, the ESD devices have limited ability to discharge electrostatic charges due to the lattice structure of the polycrystalline silicon layer. Thus, raising the ability of the ESD devices to discharge the electrostatic charges in the power semiconductor devices is an objective in this field.